Synchronization design of a coupled phase-locked loop

Coupled phase-locked loops (CPLLs) are introduced as novel circuits for phased-array antennas. Successful implementation relies on characterizing the synchronization behavior of CPLL circuits over a broad range of circuit parameters. Considering inherent time delay in the phase-locked loop demonstrates the degradation in the pull-in and hold-in ranges, as well as circuit instabilities, suggesting circuit parameter limits in a phased-array design. We compare the theoretical limits, in the form of analytic equations and numerical simulations, with measurements of the pull-in and hold-in processes of a 1.5-GHz prototype CPLL.