Linearity analysis of CMOS for RF application

The linearity of CMOS has been analyzed using the Taylor series. Transconductance and output conductance are two dominant nonlinear sources of CMOS. At a low frequency, the transconductance is a dominant nonlinear source for a low load impedance, but for a usual operation level impedance the output conductance is a dominant nonlinear source. Capacitances and the substrate network do not generate any significant nonlinearity, but they suppress output-conductance nonlinearity at a high frequency because output impedance is reduced by the capacitive shunts, and output voltage swing is also reduced. Therefore, above 2-3 GHz, the transconductance becomes a dominant nonlinear source for a usual load impedance. If these capacitive elements are tuned out for a power match, the behavior becomes similar to the low-frequency case. As gate length is reduced, the transconductance becomes more linear, but the output conductance becomes more nonlinear. At a low frequency, CMOS linearity is degraded as the gate length becomes shorter, but at a higher frequency (above 2-3 GHz), linearity can be improved.