Title of article
50-gbit/s InP HEMT 4 : 1 multiplexer/1 : 4 demultiplexer chip set with a multiphase clock architecture
Author/Authors
T.، Enoki, نويسنده , , H.، Sugahara, نويسنده , , S.، Sugitani, نويسنده , , K.، Sano, نويسنده , , K.، Murata, نويسنده , , H.، Kitabayashi, نويسنده ,
Issue Information
روزنامه با شماره پیاپی سال 2003
Pages
-2547
From page
2548
To page
0
Abstract
A 50-Gbit/s InP high electron-mobility transistor (HEMT) chip set of 4 : 1 multiplexer (MUX) and 1 : 4 demultiplexer (DMUX) integrated circuits (ICs) with a multiphase clock (MPC) architecture is described. The MPC architecture employs a quarter-rate four-phase clock generated by a toggle flip-flop inside the ICs, which reduces the number of circuit elements and lowers the power consumption. The fabricated 4 : 1 MUX and 1 : 4 DMUX ICs exhibited 50Gbit/s error-free operations for 2/sup 31/-1 pseudorandom bit sequences with 1.71- and 1.42-W power consumption, respectively. Compared to conventional tree-type 4 : 1 MUX and 1 : 4 DMUX ICs using InP HEMTs, the MPC 4 : 1 MUX and 1 : 4 DMUX ICs operate at the same operating speed with less than one-third power consumption.
Keywords
rectangular waveguide (RWG) , waveguide transition , Laminated waveguide , low-temperature co-fired ceramic (LTCC) , millimeter wave
Journal title
IEEE Transactions on Microwave Theory and Techniques
Serial Year
2003
Journal title
IEEE Transactions on Microwave Theory and Techniques
Record number
85964
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