Maximum mean weight cycle in a digraph and minimizing cycle time of a logic chip Original Research Article

The maximum mean weight cycle problem is well-known: given a digraph G with weights c : E(G)→R, find a directed circuit in G whose mean weight is maximum. Closely related is the minimum balance problem: Find a potential π : V(G)→R such that the numbers slack(e)≔π(w)−π(v)−c((v,w)) (e=(v,w)∈E(G)) are optimally balanced: for any subset of vertices, the minimum slack on an entering edge should equal the minimum slack on a leaving edge. Both problems can be solved by a parametric shortest path algorithm. We describe an application of these problems to the design of logic chips. In the simplest model, optimizing the clock schedule of a chip to minimize the cycle time is equivalent to a maximum mean weight cycle problem. It is very important to find a solution with well-balanced slacks; this problem, in the simple model, is a minimum balance problem. However, in practical situations many constraints have to be taken into account. Therefore minimizing the cycle time and finding the optimum slack distribution are more general problems. We show how a parametric shortest path algorithm can be extended to solve these problems efficiently. Computational results with recent IBM processor chips show that the cycle time reduces considerably. Moreover, the number of critical paths (with small slack) decreases dramatically. As a result we obtain significantly faster chips. The running time of our algorithm is reasonable even for very large designs.