Author/Authors :
O.، Mutlu, نويسنده , , J.، Stark, نويسنده , , C.، Wilkerson, نويسنده , , Y.N.، Patt, نويسنده ,
Abstract :
An instruction window that can tolerate latencies to DRAM memory is prohibitively complex and power hungry. To avoid having to build such large windows, runahead execution uses otherwise-idle clock cycles to achieve an average 22 percent performance improvement for processors with instruction windows of contemporary sizes. This technique incurs only a small hardware cost and does not significantly increase the processorʹs complexity.