Author/Authors :
S.S.، Mukherjee, نويسنده , , C.T.، Weaver, نويسنده , , J.، Emer, نويسنده , , S.K.، Reinhardt, نويسنده , , T.، Austin, نويسنده ,
Abstract :
Processor designers need accurate estimates of soft-error rates early in the design cycle to make appropriate cost-reliability tradeoffs. Here, the authors present a method for estimating the architectural vulnerability factor—the probability that a fault in a particular structure will result in an error.
