Title of article
Fast fault simulation for nonlinear analog circuits
Author/Authors
N.، Engin, نويسنده , , H.G.، Kerkhoff, نويسنده ,
Issue Information
روزنامه با شماره پیاپی سال 2003
Pages
-3
From page
4
To page
0
Abstract
A new method of transient fault simulation uses dc bias grouping of faulty circuits and decreases the number of Newton-Raphson iterations needed to reach a solution. An experimental tool implementing this method achieves a speedup of 20% to 30% on a flat netlist.
Keywords
leukemia
Journal title
IEEE Design and Test of Computers
Serial Year
2003
Journal title
IEEE Design and Test of Computers
Record number
90272
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