Author/Authors :
A.، Benso, نويسنده , , S.، Di Carlo, نويسنده , , P.، Prinetto, نويسنده , , Y.، Zorian, نويسنده ,
Abstract :
HD/sup 2/BIST - a complete hierarchical framework for BIST scheduling, data-patterns delivery, and diagnosis of complex systems - maximizes and simplifies the reuse of builtin test architectures. HD/sup 2/BIST optimizes the flexibility for chip designers in planning an overall SoC test strategy by defining a test access method that provides direct virtual access to each core of the system.
