The design of optimal planar systolic arrays for matrix multiplication

The objective of this paper is to provide a systematic methodology for the design of space-time optimal pure planar systolic arrays for matrix multiplication. The procedure is based on data dependence approach. By the described procedure, we obtain ten different systolic arrays denoted as S1 to S10 classified into three classes according to interconnection patterns between the processing elements. Common properties of all systolic array designs are: each systolic array consists of n2 processing elements, near-neighbour communications, and active execution time of 3n − 2 time units. Compared to designs found in the literature, our procedure always leads to systolic arrays with optimal number of processing elements. The improvement in space domain is not achieved at the cost of execution time or PEs complexity. We present mathematically rigorous procedure which gives the exact ordering of input matrix elements at the beginning of the computation. Examples illustrating the methodology are shown.