Author/Authors :
W.K.، Kahn, نويسنده , , N.، Pesonen, نويسنده , , R.A.، Allen, نويسنده , , M.W.، Cresswell, نويسنده , , M.E.، Zaghloul, نويسنده ,
Abstract :
This paper describes a novel approach to the application of conformal mapping to capacitance evaluation. A particular structure composed of an array of identical lines and located below a conductive plate is studied. Results show the application of conformal mapping can reduce computing time when using three-dimensional electrostatic modeling and it can be the basis of algorithms of practical applications, especially in the semiconductor industry.