Fault tolerance in systems design in VLSI using data compression under constraints of failure probabilities

The design of space-efficient support hardware for built-in self-testing (BIST) is of critical importance in the design and manufacture of VLSI circuits. This paper reports new space compression techniques which facilitate designing such circuits using compact test sets, with the primary objective of minimizing the storage requirements for the circuit under test (CUT) while maintaining the fault coverage information. The compaction techniques utilize the concepts of Hamming distance, sequence weights, and derived sequences in conjunction with the probabilities of error occurrence in the selection of specific gates for merger of a pair of output bit streams from the CUT. The outputs of the space compactor may eventually be fed into a time compactor (viz. syndrome counter) to derive the CUT signatures. The proposed techniques guarantee simple design with a very high fault coverage for single stuck-line faults, with low CPU simulation time, and acceptable area overhead. Design algorithms are proposed in the paper, and the simplicity and ease of their implementations are demonstrated with numerous examples. Specifically, extensive simulation runs on ISCAS 85 combinational benchmark circuits with FSIM, ATALANTA, and COMPACTEST programs confirm the usefulness of the suggested approaches under conditions of stochastic independence as well as dependence of single and double line output errors. A performance comparison of the designed space compactors with conventional linear parity tree space compactors as benchmark is also presented, which demonstrates improved tradeoff for the new circuits between fault coverage and the CUT resources consumed contrasted with existing designs, thereby aiding to fully appreciate the enhancements.