Title of article
Simulation facilities for risc processors data flow and performance optimizations
Author/Authors
O. Starostenko، نويسنده , , A. Sanchez Aguilar، نويسنده , , S. Lobato، نويسنده ,
Issue Information
ماهنامه با شماره پیاپی سال 1997
Pages
4
From page
109
To page
112
Abstract
Direct hardware model simulation of implemented instruction set and data flow into microprocessor core permits to detect pipeline hazards, deadlocks, misses for all possible instruction streams. Characteristics of POWER RISC simulation model for performance optimization of Power PC 603 microprocessor are reviewed in this report.
Keywords
data flow , transfer equation , hardware optimization , Pipeline , RISC
Journal title
Computers & Industrial Engineering
Serial Year
1997
Journal title
Computers & Industrial Engineering
Record number
924849
Link To Document