Number shortening algorithms Original Research Article

This manuscript investigates a fundamental computational process—the shortening of floating point mantissas. One particularly surprising and useful result is the proof that a special version of bias removal (which can be executed with the swiftness of chopping) yields virtually the same error as does the symmetric rounding used in the IEEE floating point standards. This suggests that the execution speed of current floating point chips could be increased without detriment to their error behavior. Shortening errors are analyzed both stochastically and by bounds. A comparison of worst-case versus typical-case errors yields general-purpose principles which are potentially helpful guidelines for users and architects.