A novel algorithm for high-throughput programming of multilevel flash memories

This paper presents a new method to program multilevel (ML) flash memories that combines ramped-gate programming with minimum verification of the sense transistor threshold voltage, in order to achieve high program throughput, i.e., number of bits programmed per second. Such a method is studied by means of extensive measurements on production quality test chips and is found able to allow a program throughput about three times as large as the state of the art presented in the literature. Furthermore, it is found adequate for 3-bit-per-cell multilevel schemes, while for the extension to the 4-bit-per-cell case the use of error correcting codes cannot be avoided.