Analysis of the specific on-resistance of vertical high-voltage DMOSFETs on SOI

Integration of high-voltage devices on SOI substrates with deep trench isolation offers the possibility to combine low-voltage circuitry and high-voltage devices on the same chip. However, due to the buried oxide, all device contacts have to be on top of the silicon. Consequently the on-resistance does not scale in the same manner as for conventional vertical devices. In this paper, an analytical model is developed, which accurately predicts the specific on-resistance and its dependency on the number of cells. It is shown that the model predicts an optimum number of cells for a minimal specific on-resistance.