Author/Authors :
J.Y.-C.، Sun, نويسنده , , Su، Hung-Der نويسنده , , Chiou، Bi-Shiou نويسنده , , Wu، Shien-Yang نويسنده , , Chang، Ming-Hsung نويسنده , , Lee، Kuo-Hua نويسنده , , Chen، Yung-Shun نويسنده , , Chao، Chih-Ping نويسنده , , See، Yee-Chaung نويسنده ,
Abstract :
Small gate area with short gate length reduces the C-V distortion of ultrathin oxide devices, but results in high parasitic capacitance/total capacitance ratio. The floating well method can exclude the parasitic capacitance to obtain accurate inversion oxide thickness without using any dummy pattern. It is suitable for nano technology.
Keywords :
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