Simulating program disturb faults in flash memories using SPICE compatible electrical model

Electrical simulation is an important tool that enables designers to evaluate different design alternatives and assess their performance. In memory technology, these tools are used to study the performance of different cell structures and implementations. In this paper we use such simulations to study the impact of defects on the performance of flash memory bitcells. In particular, using a device level simulator, we develop a SPICE compatible model to simulate the operation of a 1T flash bitcell. We then describe a fault injection technique that can be used, in conjunction with the model, to simulate faulty cell behavior. The model is used to simulate different defects in the oxide layer of the flash core memory element. The impact of defects on bitcell behavior under disturb and normal operations is investigated and evaluated. The model is demonstrated to be valuable to evaluate the appropriateness of the logic tests and stress tests used to detect such defects in flash memories.