Title of article :
Design guideline for minimum channel length in silicon-on-insulator (SOI) MOSFET
Author/Authors :
A.، Kawamoto, نويسنده , , H.، Mitsuda, نويسنده , , Y.، Omura, نويسنده ,
Issue Information :
روزنامه با شماره پیاپی سال 2003
Pages :
-2302
From page :
2303
To page :
0
Abstract :
This brief proposes a preliminary design guideline for the minimum channel length in silicon-on-insulator (SOI) MOSFETs that is based on simulations of device characteristics. The simulations examine a wide variation in many device parameters to comprehensively evaluate device characteristics. A characteristic parameter that can successfully describe the minimum channel length is found. It is suggested that a sub-20nm-channel single-gate SOI MOSFET with suppressed short-channel effects can be stably realized by optimizing its device parameters.
Keywords :
channel hot electron (CHE) , device scaling , channel initiated secondary electron (CHISEL) , Flash electrically erasable programmable read-only memories (EEPROMs) , hot carriers , programming efficiency , Monte Carlo simulation
Journal title :
IEEE TRANSACTIONS ON ELECTRON DEVICES
Serial Year :
2003
Journal title :
IEEE TRANSACTIONS ON ELECTRON DEVICES
Record number :
95944
Link To Document :
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