Optimizing the operation sequence of a chip placement machine using TSP model

Surface mount component placement machines are being widely used in electronic manufacturing industry for automated placement of components on printed wire boards (PWBs). Their performance is determined by their board assembly time. Factors that determine this include the machineʹs architecture and placement sequence algorithm, and component locations on the board. For a given machine and a board, the assembly time can be improved by optimizing the placement sequence algorithm. This paper presents a formulation and solution of the assembly time optimization problem for the FUJI FCP-IV component placement machine. The formulation gives a mathematical description of the assembly time that can be optimized as an integer programming problem. A nearoptimal solution that can be obtained in a computationally efficient manner has been obtained by relaxing the problem to an instance of the traveling salesman problem (TSP). Simulation has been conducted on some actual boards and the results have been compared with those obtained by the actual runs at Lexmark, Inc., Lexington, KY. This shows that significant reduction in component placement time can be achieved by the proposed optimization algorithm.