Title of article :
Steiner tree optimization for buffers, blockages, and bays
Author/Authors :
S.S.، Sapatnekar, نويسنده , , C.J.، Alpert, نويسنده , , S.T.، Quay, نويسنده , , G.، Gandham, نويسنده , , Hu، Jiang نويسنده , , J.I.، Neves, نويسنده ,
Issue Information :
روزنامه با شماره پیاپی سال 2001
Pages :
-555
From page :
556
To page :
0
Abstract :
Timing optimization is a critical component of deep submicrometer design and buffer insertion is an essential technique for achieving timing closure. This work studies buffer insertion under the constraint that the buffers either: (1) avoid blockages or (2) are contained within preassigned buffer bay regions. We propose a general Steiner-tree formulation to drive this application and present a maze-routing-based heuristic that either avoids blockages or finds buffer bays. We show that the combination of our Steiner-tree optimization with leading-edge buffer-insertion techniques leads to effective solutions on industry designs
Keywords :
Power-aware
Journal title :
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
Serial Year :
2001
Journal title :
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
Record number :
97940
Link To Document :
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