Abstract :
We propose a new global routing area estimation approach for high-performance very large scale integration and multichip modules (MCMs). The objective is to route nets with minimum density of global cells, producing a four-bend routing for each two-terminal net. We propose an approximate upper bound on global cell dR<=;2d 0log(m/(2d0)), in an m*m two-dimensional array, where d0 is the estimated lower-bound density. The total wirelength is (2(alpha)+(beta))4m2d0/3, where (alpha)+(beta)=1 and (alpha) is the percentage of diagonal combinations and (beta) is the percentage of adjacent combinations of nets. If (alpha)<=(beta) (this assumption holds since a good placement minimizes the longer wires), then the total wirelength is at most 2m2d0. By counting on the adjacent and diagonal combinations separately in the cost function, dR<=[4d0/3]*log([m/(4d0/3)]). We verified that the bound obtained are realistic in the worst case. A solution to this problem can be used for quick estimation of necessary wiring space (for standard cell array designs) and difficulty of routing (for gate array designs) in the early design planning stage
