Efficient implementation of a planar clock routing with the treatment of obstacles

This paper presents a set of techniques for developing a planar clock routing with the treatment of obstacles in high speed VLSI design. The planar clock routing framework has two key components. The first component employs a cutting-line embedding (CLE) routine algorithm to construct a planar clock tree topology. The routing constructed by CLE contains crossings over the obstacles in the presence of obstacles. Thus, the second component is a planar obstacle-avoiding (POA) routing scheme to clean up those crossings. These two schemes together give a good enhancement in convenient usage and performance to build a planar clock routing