A bipartition-codec architecture to reduce power in pipelined circuits

This paper proposes a new approach to synthesize pipelined circuits with low-power consideration. We treat each output value of a combinational circuit as one state of a finite-state machine (FSM). If the output of a combinational circuit transits mainly among some few states, we could extract those states (output) and the corresponding input to build a subcircuit. After bipartitioning the circuit, we apply the encoding technique to the highly active subcircuit for further power reduction. In this paper, we formulate the bipartition problem and present a probabilistic-driven algorithm to bipartition a circuit so as to minimize the power dissipation. Our experimental results show that an average power reduction on several Microelectronic Center of North Carolina (MCNC) benchmarks of 31.6% is achievable