Selective epitaxial Si based layers and TiSi2 deposition by integrated chemical vapor deposition

High performance IC manufacturing requirements, such as large diameter wafer uniformity, reproducibility, throughput and reliability can be fulfilled by commercial integrated processing, single wafer cluster tools. This paper presents results obtained on an industrial cluster reactor for 200 mm wafers by combining epitaxial silicon related materials and selective deposition of TiSi2. Low temperature epitaxial Si and SiGe alloys are studied for buried thin layers used in CMOS and HBT devices. The doping profile abruptness for B and P are within SIMS resolution limits. TheTiSi2/Si selective deposition is also investigated, sequentially and in situ, as a technique for future salicidedS/D with a reduction in technological steps and interface contamination. Statistical electrical results obtained using 0.35 and 0.25 μm CMOS technologies in which the CVD silicide deposition is tested, are presented and compared with the standard salicide technique.