Vertical 100 nm Si-p channel JFET grown by selective epitaxy

We have fabricated a vertical silicon junction field-effect transistor (JFET) with a SiO2/polysilicon/SiO2 gate structure. Due to the vertical structure the polysilicon gate length can be easily controlled in the sub-100 nm region. The SiO2 layers below and above the gate reduce the gate-drain and gate-source capacitance due to the relatively low dielectric constant of the SiO2. In addition the SiO2 above the gate structure allows the use of selective epitaxy. The channel length of the devices was varied from 0.6 μm down to 0.3 μm leading to an improvement of the transconductance and output conductance. A transconductance of 51 mS/mm was achieved for a channel length of 0.4 μm.