Title of article
Formal verification of timed systems: a survey and perspective
Author/Authors
Wang، Farn نويسنده ,
Issue Information
روزنامه با شماره پیاپی سال 2004
Pages
-1282
From page
1283
To page
0
Abstract
An overview of the current state of the art of formal verification of real-time systems is presented. We discuss commonly accepted models, specification languages, verification frameworks, state-space representation schemes, state-space construction procedures, reduction techniques, pioneering tools, and finally some new related issues. We also make a few comments according to our experience with verification tool design and implementation.
Keywords
embedded systems , formal methods , formal verification , models , real-time systems , Specification , Temporal logics , Theory , TOOLS
Journal title
Proceedings of the IEEE
Serial Year
2004
Journal title
Proceedings of the IEEE
Record number
99574
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