Author/Authors :
C.L.، Chen, نويسنده , , C.H.، CHEN نويسنده , , Y.K.، Fang, نويسنده , , S.F.، Ting, نويسنده , , C.W.، Yang, نويسنده , , W.D.، Wang, نويسنده , , S.F.، Chen, نويسنده , , J.Y.، Cheng, نويسنده , , M.F.، Wang, نويسنده , , L.G.، Yao, نويسنده , , T.L.، Lee, نويسنده , , S.C.، Chen, نويسنده , , C.H.، Yu, نويسنده , , M.S.، Liang, نويسنده ,
Abstract :
In this work, the thermal annealing at 720(degree)C for 2 hr (called boron uphill treatment) with an SiO/sub 2/-capped layer was applied after source/drain extensions (SDE) implantation to improve the short channel characteristics of a 0.1-(mu)m PMOSFET with an ultra-low temperature nitride spacer. The influence and the mechanism of the capped layer on this uphill treatment were investigated. The results show that the capped layer treatment indeed leads to a shallower junction, improved V/sub th/ roll-off characteristic, and added immunity against subsurface punchthrough.
