Challenges for the characterization and integration of high-k dielectrics

The integration of advanced gate dielectric materials into complementary metal-oxide-semiconductor (CMOS) technology presents several significant challenges. Moreover, the introduction of these materials is expected to occur at an unprecedented pace to meet industry technology forecasts. Although recent research has focused on the search for a material that yields a suitable (higher) dielectric constant than the industry benchmark SiO2, a more important problem is the actual integration of any new dielectric material in existing CMOS flows in a cost-effective manner. These integration issues include etching, constituent stability, control of phase segregation and crystallization, dopant penetration, as well as gate electrode compatibility, which influence the resultant electrical properties. This paper reviews recent studies on some of these integration issues and the associated challenges that must be addressed for successful high-k gate dielectric integration. # 2004 Published by Elsevier B.V.