Title of article :
Fully-depleted SOI devices with TaSiN gate, HfO/sub 2/ gate dielectric, and elevated source/drain extensions
Author/Authors :
A.، Bremler-Barr, نويسنده , , A.، Vandooren, نويسنده , , L.، Mathew, نويسنده , , T.R.، White, نويسنده , , S.، Egley, نويسنده , , D.، Pham, نويسنده , , M.، RZavala, نويسنده , , S.، Samavedam, نويسنده , , J.، Schaeffer, نويسنده , , J.، Conner, نويسنده , , B.-Y.، Nguyen, نويسنده , , Jr.، White, B.E., نويسنده , , M.K.، Orlowski, نويسنده , , J.، Mogab, نويسنده ,
Issue Information :
روزنامه با شماره پیاپی سال 2003
Pages :
-341
From page :
342
To page :
0
Abstract :
We report for the first time the performance of ultrathin film fully-depleted (FD) silicon-on-insulator (SOI) CMOS transistors using HfO/sub 2/ gate dielectric and TaSiN gate material. The transistors feature 100-150 A silicon film thickness and selective epitaxial silicon growth in the source/drain extension regions. TaSiN-gate shows good threshold voltage control using an undoped channel, which reduces threshold voltage variation with silicon film thickness and discrete, random dopant placement. Device processing for CMOS fabrication is drastically simplified by the use of the same gate material for both n- and p-MOSFETs. Electrical characterization results illustrate the combined impact of using high-k dielectric and metal gate on the performance of ultrathin film FD SOI devices.
Keywords :
Analytical and numerical techniques , natural convection , heat transfer
Journal title :
IEEE Electron Device Letters
Serial Year :
2003
Journal title :
IEEE Electron Device Letters
Record number :
99973
Link To Document :
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