Title of article
A fast lock digital phase-locked-loop architecture for wireless applications
Author/Authors
M.I.، Elmasry, نويسنده , , A.M.، Fahim, نويسنده ,
Issue Information
روزنامه با شماره پیاپی سال 2003
Pages
-62
From page
63
To page
0
Abstract
A fast lock digital phase-locked-loop (PLL) frequency synthesizer for wireless applications is reported. The main advantages of the architecture include small area and digitally selectable frequency resolution. Also, a fully digital solution to reducing the phase lock time is introduced. This work is also supported by a nonlinear analytical analysis of the locking mechanism for PLLs.
Keywords
heat transfer , natural convection , Analytical and numerical techniques
Journal title
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II:ANALOG AND DIGITAL SIGNAL PROCESSING
Serial Year
2003
Journal title
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II:ANALOG AND DIGITAL SIGNAL PROCESSING
Record number
99993
Link To Document