Title :
Design Verification for Sequential Systems at Various Abstraction Levels
Author :
G. Q. Lu استاد مشاور , Joseph G. Tront استاد مشاور , Michael S. Hsiao استاد راهنما
University :
Virginia Polytechnic Institute and state University
Major :
PhD )Electrical and Computer Engineering(
Keyword :
Bounded Model Checking , Formal verification , SIMULATION , Sat , ATPG
