DocumentCode :
12010
Title :
A Scaleable FIR Filter Implementation Using 32-bit Floating-Point Complex Arithmetic on a FPGA Base Custom Computing Platform
Author :
Peter Athanas استاد راهنما , Mark Jones استاد مشاور , Nathaniel Davis IV استاد مشاور
University :
Virginia Polytechnic Institute and state University
Grade :
نامعلوم
Major :
Master of Science )Electrical Engineering(
Number of pages :
0
Publish Date :
1998
Keyword :
reconfigurable computing , digital signal processing , FIR filters
Note :
01
Language :
انگليسي
Link To Document :
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