DocumentCode :
30354
Title :
Instruction Scheduling to Hide Loan/store Latency in Irregular Architecture Embedded Processors
Author :
Santosh Pande استاد راهنما
University :
OhioLINK ETD
Grade :
نامعلوم
Major :
MS )University of Cincinnati, Engineering : Computer Engineering(
Number of pages :
0
Publish Date :
2001
Keyword :
DSP , VLIW , Dynamic Scheduling , Just In Time )JTT( Scheduling , Compiler Optimization
Note :
01
Language :
انگليسي
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=17&DC=30354
