Design and Modeling of Systolic Array Based on VHDL and FPGA

Systolic array design based on Field Programmable Gate Array (FPGA ) can be adapted to efficiently resolve a wide spectrum of computational problems; parallelism, which is also naturally explored in systolic array and in implementing this design in FPGA, allows the redefinition of the interconnections and operations even during run time (dynamically).We have designed D systolic array architecture that implements the matrix multiplication algorithm. A VHDL for this design is applied to Xilinx FPGA. This design would be faster than the software of any alternative algorithm.