شماره ركورد كنفرانس :
1730
عنوان مقاله :
A Power-Efficient Successive Approximation ADC Using an Improved Control Logic Circuit
عنوان به زبان ديگر :
A Power-Efficient Successive Approximation ADC Using an Improved Control Logic Circuit
پديدآورندگان :
Masoodian Saleh نويسنده , A. Khalatbari Mohsen نويسنده
كليدواژه :
digital logic , Analog to digital converter; Digital logic; Powerefficiency; Successive approximation register , Successive approximation register , Powerefficiency , Flip-flops , analog to digital converter
عنوان كنفرانس :
بيستمين كنفرانس مهندسي برق ايران
چكيده لاتين :
In this paper a new control logic circuit for successive approximation register analog-to-digital converter (SA-ADC) is proposed. In the proposed digital circuit architecture, thenumber of flip-flops is reduced and the flip-flops do not need set and reset nodes. The simulation results of a 5-bit, 100 MS/s ADCin a 0.18-μm technology show that the digital power consumption of the proposed structure is reduced by a factor of 17% and the overall power consumption is reduced around 10% incomparison with the conventional counterpart.
شماره مدرك كنفرانس :
4460809
