A novel divided encoder with MOS CML multiplexers in a flash ADC

In this paper a novel structure of two-segment encoder with MOS current mode logic (MCML) multiplexers is presented. By assistance of these multiplexers, each segment encodes the most significant bits (MSBs) and the least significant bits (LSBs), separately. The number of required multiplexers is low, so there are fewer mismatches especially in high frequency and resolution. Also, both the number of inputs and outputs of each segment of the proposed encoder are fewer than the number of them in a conventional encoder. Hence, to remove the bubble errors and metastability, the complicated algorithms aren’t needed. Also, the structure of the proposed encoder in high-resolution flash ADC is simpler. In this paper, a 6-bit 1.5GS/s flash ADC is simulated in a 0.18μm digital CMOS technology. The results of simulations are as follows: signal-to-noise-and-distortion ratio (SINAD), power dissipation and figure of merit (FOM) are 37.62dB, 21mW and 0.225 pJ/conversion-step, respectively.