High Performance Hybrid-switched Network-on-Chip Using Shortcut Paths

The ever increasing core count in multiprocessor systems-on-chip highlights the importance of on chip networks in managing the inter-core communication. In particular, two main concerns in designing such communication systems are delay and power consumption. In this paper, a hybrid packet-circuit switching for networks-on-chip is represented that features the main benefits of both basic switching techniques: the scalability of packet-switching and superior power-efficacy of circuitswitching. This architecture reduces power consumption by setting up circuit-like shortcut paths for packets. Travelling on pre-reserved shortcut paths, packets bypass the intermediate routers, effectively eliminating the power and time that the conventional packet-switching would consume. The proposed method uses the Time-Division Multiplexing (TDM) scheme to share network bandwidth between shortcut and regular packetswitched paths. The proposed architecture relies on a global network, called Setup Network (Snet), to construct shortcut paths. The simulation results show that this method increases the packet-switching performance by up to 35%.