شماره ركورد كنفرانس :
3926
عنوان مقاله :
Implementation of Low-Power and High- Performance Asynchronous Dual-Rail Join Using Domino Logic Gates in 16-nm Technology
پديدآورندگان :
Rezaei Hossein ho_rezaei@elec.iust.ac.ir Department of Electrical Engineering and Electronics Research Center, Iran University of Science and Technology, Tehran, Iran , Aghli Moghaddam Soodeh saghli@iust.ac.ir Department of Electrical Engineering and Electronics Research Center, Iran University of Science and Technology, Tehran, Iran
كليدواژه :
asynchronous circuits , join , asynchronous join , dynamic logic , domino logic , dual , rail , ptm 16 , nm ,
عنوان كنفرانس :
بيست و چهارمين كنفرانس مهندسي برق ايران
چكيده فارسي :
Th is paper presents a transistor level circuit design for an Asynchronous Dual-Rail Domino Join (ADRDJ) using PTM 16-nm model at 0.7 V power supply. Th e ADRDJ scheme is a low-power and high-performance weakly indicating functional block. Also, it is reduced the layout congestion due to removing the clock distribution network. Simulation results for a wide sequence of inputs are shown that comparing with the synchronous counterpart, the latency and power consumption improvements are 6% and 51.8%, respectively. Also, the ADRDJ scheme is consumed 46.7% more silicon with respect to synchronous dual-rail domino join (SDRDJ). However, since the clock distribution network is removed, the overall area overhead will be reduced.
