پديدآورندگان :
Attari Sadegh sadegh.attari@ee.sharif.edu Department of Electrical Engineering, Sharif University of Technology, Tehran, Iran , Rezaei Shahmirzadi Aein rezaeishahmirzad@ee.sharif.edu Department of Electrical Engineering, Sharif University of Technology, Tehran, Iran , Salmasizadeh Mahmoud salmasi@sharif.edu Electronics Research Institute, Sharif University of Technology, Tehran, Iran , Gholampour Iman imangh@sharif.edu Electronics Research Institute, Sharif University of Technology, Tehran, Iran
كليدواژه :
Side , channel , attack , Finite state machine , Masking , Hiding
چكيده فارسي :
In this work, we present a novel FPGA-based
implementation of the AES algorithm which has a two-layered
resistance against power analysis attacks. Our countermeasure
is based on the concept of finite state machine equipped with a
random number generator. Beyond masking the intermediate
variables as the first layer of defense, we randomize the
sequences of operations and add dummy computations as
the second layer of defense. Therefore, the first order attack
is prevented and the number of power traces needed for a
successful second order attack is vastly increased and the
correlation coefficient is decreased, as expected.
