High Speed 10 Bit Segmented Current Steering DAC

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The 10 bits segmented current steering DAC in 90nm CMOS technology is investigated and simulation results are considered in this work. This architecture comprises two separated structure, one of them 4 bit binary weighted current steering and another 6 bit unit element. To reach acceptable current source variation due to the supply voltage several architecture are considered finally the presented current reference could satisfy the requirements. Thermometer coding is used to improve the performance, as one bit changes at a time so glitches and DNL are reduced. To select which current cell is on at the moment, the matrix architecture is utilized that uses fully digital operation. All digital processing units are implemented using NAND standard logic gate that may results less propagation delay time hence higher operating frequency. High gain opamp is not utilized at the output node because of its frequency limitation. To reduce the error caused by the output resistance of the current sources, cascade current sink is applied. The goal of this paper is to reach highest reasonable input update rate. Finally at 200MHz input word update rate |DNL|=0.26 LSB and |INL|=1.2 LSB are achieved. Total power consumption is 10.77 mW.