The Improvement of Voltage Reference below 1V with Low Temperature Dependence and Resistant to Variations of Power Supply in CMOS Technology

The Improvement of Voltage Reference below 1V with Low Temperature Dependence and Resistant to Variations of Power Supply in CMOS Technology

In this article, the objective is designing a linear voltage reference based on CMOS technology and a structure which is insensitive to variations of temperature and supply power. In such a case, accuracy of circuit output will be optimal under different conditions. Among such sensitivities, one could point to variation of output in relation to temperature, variation due to output performance of the structure and currents, noises and turbulence. First, different voltage references, their structures and advantages and disadvantages will be reviewed individually. Then, output startup method will be explained through bulk transistor and parallel combination of transistors in output for control of output leakage current. This is followed by elaboration of reference building designed based on this method. Consequently, intended structure will designed by taking above-mentioned objectives into account. The circuit simulation and circuit layout will be done through H-Spice Software and Cadence applications respectively. The pre-layout and post-layout results signify improved results and resistance of suggested circuit against substrate noise and noise of power supply. Simulations will be done through 0.18um CMOS technology.

In this article, the objective is designing a linear voltage reference based on CMOS technology and a structure which is insensitive to variations of temperature and supply power. In such a case, accuracy of circuit output will be optimal under different conditions. Among such sensitivities, one could point to variation of output in relation to temperature, variation due to output performance of the structure and currents, noises and turbulence. First, different voltage references, their structures and advantages and disadvantages will be reviewed individually. Then, output startup method will be explained through bulk transistor and parallel combination of transistors in output for control of output leakage current. This is followed by elaboration of reference building designed based on this method. Consequently, intended structure will designed by taking above-mentioned objectives into account. The circuit simulation and circuit layout will be done through H-Spice Software and Cadence applications respectively. The pre-layout and post-layout results signify improved results and resistance of suggested circuit against substrate noise and noise of power supply. Simulations will be done through 0.18um CMOS technology.