DMR-based Technique for Fault Tolerant AES S-box Architecture

This paper presents a high-throughput fault-resilient hardware implementation of AES S-box, called HFS-box. We propose deep pipelining S-box in the gate level in which a novel DMR technique is used for fault correction. Proposed fault-resilient technique is based on fault correction in DMR implementation (FC-DMR) of each S-box’s combined with a temporal redundancy technique. If a transient natural or even malicious fault(s) in each pipeline stage is detected, the corresponding error signal become high and as a result the control unit holds the output of our proposed DMR voter till the fault effect disappears. Proposed low-cost HFS-box provide a high capability of fault tolerant against transient faults with any duration by putting low area overhead, i.e. 137%, and low throughput degradation, i.e. 11.3%, on the original implementation.