شماره ركورد كنفرانس :
2727
عنوان مقاله :
A FGMOS-Based Four-Quadrant Current Multiplier with Reduced Power Dissipation
عنوان به زبان ديگر :
A FGMOS-Based Four-Quadrant Current Multiplier with Reduced Power Dissipation
پديدآورندگان :
Moradinezhad Maryan Mohammad نويسنده Iran University of Science and Technology (IUST) - Department of Electrical and Electronics Engineering , Hajipour Mohammadreza نويسنده Iran University of Science and Technology (IUST) - Department of Electrical and Electronics Engineering , Kamyar Abbas نويسنده Iran University of Science and Technology (IUST) - Department of Electrical and Electronics Engineering
كليدواژه :
current squarer , saturation region , floating-gate MOS , four-quadrant multiplier
عنوان كنفرانس :
اولين كنفرانس بين المللي دستاوردهاي نوين پژوهشي در مهندسي برق و كامپيوتر
چكيده لاتين :
In this paper, we present a novel low-power, highspeed four-quadrant analog multiplier which is based on a simple
current squarer circuit. The squarer circuit consists of a floatinggate MOS (FGMOS) transistor, operating in saturation region
and a resistor. The proposed multiplier has a balanced structure composed of four squarer cells and a simple current mirror. This multiplier also has a unique property of not using bias currents which results in greatly reduced power. For performance
evaluation, the design was simulated using HSPICE software in 0.18 μm TSMC CMOS technology. Using ±0.5 V DC supply
voltages, the simulation resulted in the maximum linearity error of 0.8%, the -3dB bandwidth of 635 MHz, the Total Harmonic
Distortion (THD) of 0.57% (at 1 MHz), and maximum and static power consumptions of 24 μW and 5.75 μW, respectively.
Furthermore, to verify the robustness and reliability of the proposed work, Monte Carlo analysis was performed. For this
analysis, 5% variations in channel width and length, gate oxide thickness and threshold voltage of all transistors and resistance values were considered.
شماره مدرك كنفرانس :
4240260
