IMPLEMENTATION OF THE FPGA BASED PROGRAMMABLE EMBEDDED INTRUSION DETECTION SYSTEM

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In this paper, an embedded Intrusion Detection System (IDS) running in the real time has been implemented. The implemented system is based on System On Programmable Chip (SOPC) to classify the captured packet from the network. IEEE 802.3 standard frames have been captured with 10/100 Ethernet MAC Core programming of the processor used in the system. Each captured frame has stored to the memory of the embedded IDS for the determination of packet classes from obtained frames. The processor has been programmed to determine the packet classification and to obtain the packet summaries and the packets from frames. Artifical Neural Network (ANN) has been used in the classification process of the system. The inputs of ANN are obtained from the features of packet headers, such as port number and IP number. The implemented embedded IDS has been first trained with training data. Then, packet classification has been performed in the real time and finally time of determining packet classes have been obtained. The system has been implemented on Altera’s Cyclone III EPC3C40F484C7N platform and software environments.

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Intrusion Detection System , System On Programmable Chip , 10 , 100 Ethernet MAC Core

Journal Of The Faculty Of Engineering an‎d Architecture Of Gazi University

69

Journal Of The Faculty Of Engineering an‎d Architecture Of Gazi University