Title :
A Wirelist Compare Program for Verifying VLSI Layouts
Author :
Kodandapani, K.L. ; McGrath, Edward J.
Author_Institution :
Digital Equipment Corporation
fDate :
6/1/1986 12:00:00 AM
Abstract :
We will describe a wirelist compare program that, together with a VLSI node extractor, is used to verify VLSI IC layout connectivity. Engineers at Digital Equipment Corporation have successfully used this tool in a production environment to debug layout errors. The program is based on a graph isomorphism algorithm and provides graphical and textual guides to pinpoint errors. We will examine this algorithm, its error outputs, and provide run-time statistics.
Keywords :
Circuit simulation; Digital integrated circuits; Error correction; Integrated circuit interconnections; Integrated circuit layout; Integrated circuit modeling; Operating systems; Production; Very large scale integration; Voice mail;
Journal_Title :
Design & Test of Computers, IEEE
DOI :
10.1109/MDT.1986.294992
