• DocumentCode
    1000263
  • Title

    A Wirelist Compare Program for Verifying VLSI Layouts

  • Author

    Kodandapani, K.L. ; McGrath, Edward J.

  • Author_Institution
    Digital Equipment Corporation
  • Volume
    3
  • Issue
    3
  • fYear
    1986
  • fDate
    6/1/1986 12:00:00 AM
  • Firstpage
    46
  • Lastpage
    51
  • Abstract
    We will describe a wirelist compare program that, together with a VLSI node extractor, is used to verify VLSI IC layout connectivity. Engineers at Digital Equipment Corporation have successfully used this tool in a production environment to debug layout errors. The program is based on a graph isomorphism algorithm and provides graphical and textual guides to pinpoint errors. We will examine this algorithm, its error outputs, and provide run-time statistics.
  • Keywords
    Circuit simulation; Digital integrated circuits; Error correction; Integrated circuit interconnections; Integrated circuit layout; Integrated circuit modeling; Operating systems; Production; Very large scale integration; Voice mail;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/MDT.1986.294992
  • Filename
    4069793
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1000263