Title :
From substrate to VLSI: investigation of hardened SIMOX without epitaxy, for dose, dose rate and SEU phenomena
Author :
Leray, J.L. ; Dupont-Nivet, E. ; Musseau, O. ; Coïc, Y.M. ; Umbert, A. ; Lalande, P. ; Péré, J.F. ; Auberton-Herve, A.J. ; Bruel, M. ; Jaussaud, C. ; Margail, J. ; Giffard, B. ; Truche, R. ; Martin, F.
Author_Institution :
CEA, Bruyeres-Le-Chatel, France
fDate :
12/1/1988 12:00:00 AM
Abstract :
A silicon-on-insulator (SOI) technology with a hardened variant is presented, focusing on some of the weak points that could impede the progress of SOI toward the production of high-speed hardened VLSI. The devices described here use the LOCOS isolation method instead of the commonly used MESA and a thin active silicon layer on which no epitaxy takes place. Dose and dose rate tests were performed on both technologies and on various circuits and special-purpose devices. An analysis of the sensitivity of the circuits to single-event upset, (SEU) was made, and a hardness limitation coming from an ion-induced transient caused by substrate-related phenomena was found. Dose, dose rate, and SEU behavior are related to the structural characteristics mentioned above
Keywords :
VLSI; field effect integrated circuits; insulated gate field effect transistors; integrated circuit technology; radiation hardening (electronics); semiconductor technology; semiconductor-insulator boundaries; LOCOS isolation method; SEU; SEU phenomena; SIMOX; SOI; VLSI; dose phenomena; dose rate phenomena; dose rate tests; dose tests; hardened variant; hardness limitation; high-speed hardened VLSI; ion-induced transient; radiation hardened electronics; single-event upset; special-purpose devices; structural characteristics; substrate-related phenomena; weak points; Circuit testing; Epitaxial growth; Impedance; Isolation technology; Performance evaluation; Production; Silicon on insulator technology; Single event upset; Substrates; Very large scale integration;
Journal_Title :
Nuclear Science, IEEE Transactions on
