Voltage limiters for DRAMs with substrate-plate-electrode memory cells

To prevent substrate-plate-electrode (SPE) cell weakness due to substrate-bias voltage bounce, voltage limiters were applied to both the substrate and the sense-circuit supply source. A supply voltage V/sub CC/ bump test was introduced to evaluate their effectiveness. The voltage limiters have been implemented on an experimental 4-Mb DRAM. It was found that a wider operational margin, as compared to conventional DRAMs (without voltage limiters) having SPE cells, was achievable through the use of voltage limiters. These voltage limiters may be considered suitable for wide operational margin DRAMs with SPE cells. The substrate-bias voltage limiter, in particular, is more effective than the sense-circuit supply voltage limiter and offers a means of improving the operational margin of V/sub CC/ bump.<>