Post-irradiation effects in CMOS integrated circuits [SRAMs]

Author

Zietlow, T.C. ; Barnes, C.E. ; Morse, T.C. ; Grusynski, J.S. ; Nakamura, K. ; Amram, A. ; Wilson, K.T.

Volume

35

Issue

6

fYear

1988

fDate

12/1/1988 12:00:00 AM

Firstpage

1662

Lastpage

1666

Abstract

The postirradiation response of CMOS integrated circuits from three vendors was measured as a function of temperature and irradiation bias. It was found that a worst-case anneal temperature for rebound testing is highly process-dependent. At an anneal temperature of 80°C, the timing parameters of a 16 K SRAM from vendor A quickly saturate at maximum values and display no further changes at this temperature. At higher temperatures, evidence for the anneal of the interface-state charge is observed. Dynamic bias during irradiation results in the same saturation value for the timing parameters, but the anneal time required to reach this value is no longer. CMOS/SOS integrated circuits (vendor B) showed similar behavior, except that the saturation value for the timing parameters was stable up to 105°C. After irradiation to 10 Mrad(Si), a 16 K SRAM (vendor C) was annealed at 80°C, and the access time decreased toward prerad values during the anneal

Keywords

CMOS integrated circuits; annealing; integrated memory circuits; random-access storage; 105 degC; 10E6 rad; 16 kbit; 80 degC; CMOS integrated circuits; SRAM; access time; interface-state charge; irradiation bias; postirradiation response; rebound testing; saturation value; temperature; timing parameters; worst-case anneal temperature; Annealing; CMOS integrated circuits; Circuit testing; Interface states; Ionizing radiation; Laboratories; MOS devices; Random access memory; Temperature dependence; Timing;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/23.25517

Filename

25517