Experimental and analytical investigation of single event, multiple bit upsets in poly-silicon load, 64 K×1 NMOS SRAMs

Author

Song, Y. ; Vu, K.N. ; Cable, J.S. ; Witteles, A.A. ; Kolasinski, W.A. ; Koga, R. ; Elder, J.H. ; Osborn, J.V. ; Martin, R.C. ; Ghoniem, N.M.

Author_Institution

TRW Inc., Redondo Beach, CA, USA

Volume

35

Issue

6

fYear

1988

fDate

12/1/1988 12:00:00 AM

Firstpage

1673

Lastpage

1677

Abstract

Long time constants associated with extremely high pull-up resistances commonly used in high-density, polysilicon-load NMOS SRAMs were identified as the primary cause of single-event-induced, multiple-bit upsets recently observed in cyclotron tests. Diffusion currents can cause single-event errors in this long-time-constant regime. Above certain threshold linear energy transfers, multiple-bit upsets constitute almost all the single-event errors in the SRAMs. Conventionally calculated error cross-sections can be larger than the chip area and can result in unreasonably large bit error rates. A new method of defining the SEU figure-of-merit in space environments that includes multiple-bit upsets is needed

Keywords

MOS integrated circuits; integrated memory circuits; radiation effects; random-access storage; 64 kbit; NMOS SRAMs; bit error rates; chip area; cyclotron tests; error cross-sections; multiple bit upsets; poly-silicon load; pull-up resistances; single event; space environments; threshold linear energy transfers; time constants; Application software; Bit error rate; Circuits; Cyclotrons; Error analysis; MOS devices; Random access memory; Single event upset; Testing; Very large scale integration;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/23.25520

Filename

25520