Title :
Parallel processing of logic module placement
Author :
Sugiyama, Y. ; Watanabe, T.
Author_Institution :
NTT Atsugi Electrical Communication Laboratory, Atsugi, Japan
Abstract :
A parallel-processing algorithm for logic module placement is presented. A pairwise interchange algorithm, directed by the steepest-descent concept, is expanded to the parallel-processing case. By using an AAP (adaptive array processor), it is shown that an N-module placement problem can be processed in 0.06N of the time required by a sequential computer (1 MIPS).
Keywords :
circuit layout CAD; logic CAD; modules; parallel processing; AAP; N-module placement problem; PCB layout; adaptive array processor; computing time; logic module placement; monolithic chip layout; pairwise interchange algorithm; parallel-processing algorithm; steepest-descent concept; time required;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19840145
